Vengono qui proposti alcuni esercizi di programmazione del PIC 18F45K20 con il debugger/programmer PICkit3 e MPLAB X IDE.
-
Lampeggio LED
Sulla Demo Board sono presenti 8 Leds collegati alla Porta D, in questo progetto faremo lampeggiare il led 0.
I registri coinvolti sono OSCCON per le impostazioni riguardanti alla frequenza ed al tipo di Oscillatore di Clock scelto (Interno), e quelli riguardanti la gestione della Porta D, quindi TRISD per il modo di utilizzo dei pins, LATD per la scrittura dei valori in uscita sui Leds
Il file Config.h
// PIC18F45K20 Configuration Bit Settings // 'C' source line config statements // CONFIG1H #pragma config FOSC = INTIO67 // Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7) #pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled) #pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled) // CONFIG2L #pragma config PWRT = OFF // Power-up Timer Enable bit (PWRT disabled) #pragma config BOREN = OFF // Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software) #pragma config BORV = 30 // Brown Out Reset Voltage bits (VBOR set to 3.0 V nominal) // CONFIG2H #pragma config WDTEN = OFF // Watchdog Timer Enable bit (WDT is controlled by SWDTEN bit of the WDTCON register) #pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768) // CONFIG3H #pragma config CCP2MX = PORTC // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1) #pragma config PBADEN = ON // PORTB A/D Enable bit (PORTB<4:0> pins are configured as analog input channels on Reset) #pragma config LPT1OSC = ON // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for low-power operation) #pragma config HFOFST = ON // HFINTOSC Fast Start-up (HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize.) #pragma config MCLRE = OFF // MCLR Pin Enable bit (RE3 input pin enabled; MCLR disabled) // CONFIG4L #pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset) #pragma config LVP = OFF // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled) #pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode)) // CONFIG5L #pragma config CP0 = OFF // Code Protection Block 0 (Block 0 (000800-001FFFh) not code-protected) #pragma config CP1 = OFF // Code Protection Block 1 (Block 1 (002000-003FFFh) not code-protected) #pragma config CP2 = OFF // Code Protection Block 2 (Block 2 (004000-005FFFh) not code-protected) #pragma config CP3 = OFF // Code Protection Block 3 (Block 3 (006000-007FFFh) not code-protected) // CONFIG5H #pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected) #pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected) // CONFIG6L #pragma config WRT0 = OFF // Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected) #pragma config WRT1 = OFF // Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected) #pragma config WRT2 = OFF // Write Protection Block 2 (Block 2 (004000-005FFFh) not write-protected) #pragma config WRT3 = OFF // Write Protection Block 3 (Block 3 (006000-007FFFh) not write-protected) // CONFIG6H #pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected) #pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected) #pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected) // CONFIG7L #pragma config EBTR0 = OFF // Table Read Protection Block 0 (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks) #pragma config EBTR1 = OFF // Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks) #pragma config EBTR2 = OFF // Table Read Protection Block 2 (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks) #pragma config EBTR3 = OFF // Table Read Protection Block 3 (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks) // CONFIG7H #pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks) #define _XTAL_FREQ 1000000
Il file main.c
/** -------------------- PROGRAMMA LAMPEGGIO LED -------------------- **/
/* Commenti e descrizione al programma */
/** I N C L U D E S **************************************************/
#include <xc.h>
#include "Config.h"
void Setup(void) {
OSCCON = 0b00110110; // Internal Osc, 1MHz, F stabile
TRISD = 0b01111111; // PORTD bit 7 to output (0); bits 6:0 are inputs (1)
LATDbits.LATD7 = 0; // Clear LAT register bit 7 to turn off LED
}
void main (void)
{
Setup();
while (1){
LATDbits.LATD7 = 1;
__delay_ms(500);
LATDbits.LATD7 = 0;
__delay_ms(500);
};
}
- Scorrimento LEDs
In questo esercizio i registri coinvolti sono gli stessi del precedente, OSCCON per l’oscillatore di clock, TRISD e LATD per la gestione dei pins collegati ai LEDs
Il file Config.h
// PIC18F45K20 Configuration Bit Settings // 'C' source line config statements // CONFIG1H #pragma config FOSC = INTIO67 // Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7) #pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled) #pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled) // CONFIG2L #pragma config PWRT = OFF // Power-up Timer Enable bit (PWRT disabled) #pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled)) #pragma config BORV = 18 // Brown Out Reset Voltage bits (VBOR set to 1.8 V nominal) // CONFIG2H #pragma config WDTEN = OFF // Watchdog Timer Enable bit (WDT is controlled by SWDTEN bit of the WDTCON register) #pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768) // CONFIG3H #pragma config CCP2MX = PORTC // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1) #pragma config PBADEN = ON // PORTB A/D Enable bit (PORTB<4:0> pins are configured as analog input channels on Reset) #pragma config LPT1OSC = OFF // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation) #pragma config HFOFST = ON // HFINTOSC Fast Start-up (HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize.) #pragma config MCLRE = ON // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled) // CONFIG4L #pragma config STVREN = OFF // Stack Full/Underflow Reset Enable bit (Stack full/underflow will not cause Reset) #pragma config LVP = OFF // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled) #pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode)) // CONFIG5L #pragma config CP0 = OFF // Code Protection Block 0 (Block 0 (000800-001FFFh) not code-protected) #pragma config CP1 = OFF // Code Protection Block 1 (Block 1 (002000-003FFFh) not code-protected) #pragma config CP2 = OFF // Code Protection Block 2 (Block 2 (004000-005FFFh) not code-protected) #pragma config CP3 = OFF // Code Protection Block 3 (Block 3 (006000-007FFFh) not code-protected) // CONFIG5H #pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected) #pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected) // CONFIG6L #pragma config WRT0 = OFF // Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected) #pragma config WRT1 = OFF // Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected) #pragma config WRT2 = OFF // Write Protection Block 2 (Block 2 (004000-005FFFh) not write-protected) #pragma config WRT3 = OFF // Write Protection Block 3 (Block 3 (006000-007FFFh) not write-protected) // CONFIG6H #pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected) #pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected) #pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected) // CONFIG7L #pragma config EBTR0 = OFF // Table Read Protection Block 0 (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks) #pragma config EBTR1 = OFF // Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks) #pragma config EBTR2 = OFF // Table Read Protection Block 2 (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks) #pragma config EBTR3 = OFF // Table Read Protection Block 3 (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks) // CONFIG7H #pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks) #define _XTAL_FREQ 1000000
Il file main.c
/** -------------------- PROGRAMMA SCORRIMENTO LED -------------------- **/
/* Commenti e descrizione al programma */
/** I N C L U D E S **************************************************/
#include <xc.h>
#include "Config.h"
void Setup(){
OSCCON = 0b00110110; // Internal Osc, 1MHz, F stabile
TRISD = 0b00000000; // PORTD bit 7 to output (0); bits 6:0 are inputs (1)
LATD = 0b00000000; // Clear LAT register bit 7 to turn off LED
}
void main (void)
{
Setup();
while (1){
LATD = 0b00000001;
__delay_ms(100);
LATD = 0b00000010;
__delay_ms(100);
LATD = 0b00000100;
__delay_ms(100);
LATD = 0b00001000;
__delay_ms(100);
LATD = 0b00010000;
__delay_ms(100);
LATD = 0b00100000;
__delay_ms(100);
LATD = 0b01000000;
__delay_ms(100);
LATD = 0b10000000;
__delay_ms(100);
};
}
- Digital in
In questo esercizio i registri coinvolti sono, oltre a OSCCON per l’oscillatore di clock, TRISD e LATD per la gestione dei pins collegati ai LEDs, quelli che riguardano l’utilizzo di un Pulsante (Ingresso Digitale) collegato a RB0, cioè TRISB, PORTB e INTCON2 per il settaggio del Pull-Up su RB0.
// PIC18F45K20 Configuration Bit Settings // 'C' source line config statements // CONFIG1H #pragma config FOSC = INTIO67 // Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7) #pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled) #pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled) // CONFIG2L #pragma config PWRT = OFF // Power-up Timer Enable bit (PWRT disabled) #pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled)) #pragma config BORV = 18 // Brown Out Reset Voltage bits (VBOR set to 1.8 V nominal) // CONFIG2H #pragma config WDTEN = OFF // Watchdog Timer Enable bit (WDT is controlled by SWDTEN bit of the WDTCON register) #pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768) // CONFIG3H #pragma config CCP2MX = PORTC // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1) #pragma config PBADEN = OFF // PORTB A/D Enable bit (PORTB<4:0> pins are configured as analog input channels on Reset) #pragma config LPT1OSC = OFF // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation) #pragma config HFOFST = ON // HFINTOSC Fast Start-up (HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize.) #pragma config MCLRE = ON // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled) // CONFIG4L #pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset) #pragma config LVP = ON // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled) #pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode)) // CONFIG5L #pragma config CP0 = OFF // Code Protection Block 0 (Block 0 (000800-001FFFh) not code-protected) #pragma config CP1 = OFF // Code Protection Block 1 (Block 1 (002000-003FFFh) not code-protected) #pragma config CP2 = OFF // Code Protection Block 2 (Block 2 (004000-005FFFh) not code-protected) #pragma config CP3 = OFF // Code Protection Block 3 (Block 3 (006000-007FFFh) not code-protected) // CONFIG5H #pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected) #pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected) // CONFIG6L #pragma config WRT0 = OFF // Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected) #pragma config WRT1 = OFF // Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected) #pragma config WRT2 = OFF // Write Protection Block 2 (Block 2 (004000-005FFFh) not write-protected) #pragma config WRT3 = OFF // Write Protection Block 3 (Block 3 (006000-007FFFh) not write-protected) // CONFIG6H #pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected) #pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected) #pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected) // CONFIG7L #pragma config EBTR0 = OFF // Table Read Protection Block 0 (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks) #pragma config EBTR1 = OFF // Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks) #pragma config EBTR2 = OFF // Table Read Protection Block 2 (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks) #pragma config EBTR3 = OFF // Table Read Protection Block 3 (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks) // CONFIG7H #pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks) #define _XTAL_FREQ 1000000
Il file main.c
/** -------------------- PROGRAMMA DIGITAL IN -------------------- **/
/* Commenti e descrizione al programma */
/** I N C L U D E S **************************************************/
#include <xc.h>
#include "Config.h"
void Setup(void) {
TRISBbits.RB0 = 1; // Or TRISB = 0xFF;
INTCON2bits.nRBPU = 0; // Enable all input PORTB pullup
TRISD = 0b00000000; // Set RB0-RB8 come Output
OSCCON = 0b00110110; // Internal Osc, 1MHz, F stabile
}
int acq;
void main(void) {
Setup();
while(1){
if (PORTBbits.RB0 == 0){ // Pulsante premuto
LATD = 0b00000001;
__delay_ms(100);
LATD = 0b00000010;
__delay_ms(100);
LATD = 0b00000100;
__delay_ms(100);
LATD = 0b00001000;
__delay_ms(100);
LATD = 0b00010000;
__delay_ms(100);
LATD = 0b00100000;
__delay_ms(100);
LATD = 0b01000000;
__delay_ms(100);
LATD = 0b10000000;
__delay_ms(100);
}
else{
LATD = 0b00000000;
__delay_ms(100);
LATD = 0b11111111;
__delay_ms(100);
}
}
}
- PWM
Per la creazione di un Segnale PWM i registri coinvolti sono, oltre a OSCCON per l’oscillatore di clock, TRISD e LATD per la gestione dei pins collegati ai LEDs, quelli che riguardano il segnale modulato, cioè T2CON, CCP2CONe PR2.
// PIC18F45K20 Configuration Bit Settings // 'C' source line config statements // CONFIG1H #pragma config FOSC = INTIO67 // Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7) #pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled) #pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled) // CONFIG2L #pragma config PWRT = OFF // Power-up Timer Enable bit (PWRT disabled) #pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled)) #pragma config BORV = 18 // Brown Out Reset Voltage bits (VBOR set to 1.8 V nominal) // CONFIG2H #pragma config WDTEN = OFF // Watchdog Timer Enable bit (WDT is controlled by SWDTEN bit of the WDTCON register) #pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768) // CONFIG3H #pragma config CCP2MX = PORTC // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1) #pragma config PBADEN = OFF // PORTB A/D Enable bit (PORTB<4:0> pins are configured as analog input channels on Reset) #pragma config LPT1OSC = OFF // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation) #pragma config HFOFST = ON // HFINTOSC Fast Start-up (HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize.) #pragma config MCLRE = ON // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled) // CONFIG4L #pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset) #pragma config LVP = ON // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled) #pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode)) // CONFIG5L #pragma config CP0 = OFF // Code Protection Block 0 (Block 0 (000800-001FFFh) not code-protected) #pragma config CP1 = OFF // Code Protection Block 1 (Block 1 (002000-003FFFh) not code-protected) #pragma config CP2 = OFF // Code Protection Block 2 (Block 2 (004000-005FFFh) not code-protected) #pragma config CP3 = OFF // Code Protection Block 3 (Block 3 (006000-007FFFh) not code-protected) // CONFIG5H #pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected) #pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected) // CONFIG6L #pragma config WRT0 = OFF // Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected) #pragma config WRT1 = OFF // Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected) #pragma config WRT2 = OFF // Write Protection Block 2 (Block 2 (004000-005FFFh) not write-protected) #pragma config WRT3 = OFF // Write Protection Block 3 (Block 3 (006000-007FFFh) not write-protected) // CONFIG6H #pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected) #pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected) #pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected) // CONFIG7L #pragma config EBTR0 = OFF // Table Read Protection Block 0 (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks) #pragma config EBTR1 = OFF // Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks) #pragma config EBTR2 = OFF // Table Read Protection Block 2 (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks) #pragma config EBTR3 = OFF // Table Read Protection Block 3 (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks) // CONFIG7H #pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks) // Freq di osillazione #define _XTAL_FREQ 1000000
Il file main.c
/** -------------------- PROGRAMMA PWM -------------------- **/
/* Commenti e descrizione al programma */
/** I N C L U D E S **************************************************/
#include <xc.h>
#include "Config.h"
int i = 0;
int countup = 1; //our flag to set up/down dutycycle
int DutyCycle = 0;
int PWM_freq = 20000;
void Setup(void) {
TRISC = 0b11111011; // Set RC2 Output
OSCCON = 0b00110110; // Internal Osc, 1MHz, F stabile
T2CON = 0b00000100; //Prescale 1:1, Postscaler 1:1, On
CCP2CON = 0b00001100; // PWM mode
PR2 = (_XTAL_FREQ/(PWM_freq*4)) - 1; //Setting the PR2 formulae using Datasheet // Makes the PWM work in 5KHZ
}
void PWM_DC(int DutyCycle)
{
if(DutyCycle<1023) { DutyCycle = ((float)DutyCycle/1023)*(_XTAL_FREQ/(PWM_freq)); // On reducing //duty = (((float)duty/1023)*(1/PWM_freq)) / ((1/_XTAL_FREQ) * TMR2PRESCALE); DC2B1 = DutyCycle & 1; //Store the 1st bit DC2B0 = DutyCycle & 2; //Store the 0th bit CCPR2L = DutyCycle>>2;// Store the remining 8 bit
}
}
void main() {
Setup();
PWM_DC(512);
while(1) //infinite loop
{
if(countup == 1)
{
PWM_DC(DutyCycle); //Change duty cycle
DutyCycle++;
if(DutyCycle == 1024)
countup = 0;
}
else
{
PWM_DC(DutyCycle); //Change duty cycle
DutyCycle--;
if(DutyCycle == 0)
countup = 1;
}
__delay_ms(1);
}
}
- Analog In
In questo esercizio i registri coinvolti sono, oltre a OSCCON per l’oscillatore di clock, TRISD e LATD per la gestione dei pins collegati ai LEDs, quelli che riguardano l’Acquisizione Analogica, cioè TRISA, ANSEL, ADCON0, ADCON1 e ADCON2
// PIC18F45K20 Configuration Bit Settings // 'C' source line config statements // CONFIG1H #pragma config FOSC = INTIO67 // Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7) #pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled) #pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled) // CONFIG2L #pragma config PWRT = OFF // Power-up Timer Enable bit (PWRT disabled) #pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled)) #pragma config BORV = 18 // Brown Out Reset Voltage bits (VBOR set to 1.8 V nominal) // CONFIG2H #pragma config WDTEN = OFF // Watchdog Timer Enable bit (WDT is controlled by SWDTEN bit of the WDTCON register) #pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768) // CONFIG3H #pragma config CCP2MX = PORTC // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1) #pragma config PBADEN = ON // PORTB A/D Enable bit (PORTB<4:0> pins are configured as analog input channels on Reset) #pragma config LPT1OSC = OFF // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation) #pragma config HFOFST = ON // HFINTOSC Fast Start-up (HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize.) #pragma config MCLRE = ON // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled) // CONFIG4L #pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset) #pragma config LVP = ON // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled) #pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode)) // CONFIG5L #pragma config CP0 = OFF // Code Protection Block 0 (Block 0 (000800-001FFFh) not code-protected) #pragma config CP1 = OFF // Code Protection Block 1 (Block 1 (002000-003FFFh) not code-protected) #pragma config CP2 = OFF // Code Protection Block 2 (Block 2 (004000-005FFFh) not code-protected) #pragma config CP3 = OFF // Code Protection Block 3 (Block 3 (006000-007FFFh) not code-protected) // CONFIG5H #pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected) #pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected) // CONFIG6L #pragma config WRT0 = OFF // Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected) #pragma config WRT1 = OFF // Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected) #pragma config WRT2 = OFF // Write Protection Block 2 (Block 2 (004000-005FFFh) not write-protected) #pragma config WRT3 = OFF // Write Protection Block 3 (Block 3 (006000-007FFFh) not write-protected) // CONFIG6H #pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected) #pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected) #pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected) // CONFIG7L #pragma config EBTR0 = OFF // Table Read Protection Block 0 (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks) #pragma config EBTR1 = OFF // Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks) #pragma config EBTR2 = OFF // Table Read Protection Block 2 (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks) #pragma config EBTR3 = OFF // Table Read Protection Block 3 (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks) // CONFIG7H #pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks) // #pragma config statements should precede project file includes. // Use project enums instead of #define for ON and OFF. #define _XTAL_FREQ 1000000
Il file main.c
/** -------------------- PROGRAMMA Analog In-------------------- **/
/* Commenti e descrizione al programma */
/** I N C L U D E S **************************************************/
#include <xc.h>
#include "Config.h"
void Setup(void) {
TRISA = 0b00000001; // Set RA0 (aka AN0) to input
TRISD = 0b00000000; // Set RB0-RB8 come Output
OSCCON = 0b00110110; // Internal Osc, 1MHz, F stabile
ANSEL = 0b00000001; // Set AN0 (aka RA0) to analog
ADCON0 = 0b00000001; // Channel AN0 (xx00 00xx), Enable ADC (xxxx xxx1)
ADCON1 = 0b00000000; // VDD and VSS as voltage reference (xxxx 0000)
ADCON2 = 0b00111000; // Right justify result (1xxx xxx), 2 TAD delay (xx00 1xxx), TAD = 1 us (Fck/16 = 1 Mhz) (xxxx x101)
}
int acq;
void main(void) {
Setup();
while(1){
ADCON0bits.GO = 1; // Start conversione
while(ADCON0bits.GO); // Attendo finisca la conversione
acq = ADRESH; // Leggo ADC
if(acq>=0 && acq<=32) {LATD = 0b00000001;} else if(acq>32 && acq<=64) LATD = 0b00000010; else if(acq>64 && acq<=96) LATD = 0b00000100; else if(acq>96 && acq<=128) LATD = 0b00001000; else if(acq>128 && acq<=160) LATD = 0b00010000; else if(acq>160 && acq<=192) LATD = 0b00100000; else if(acq>192 && acq<=224) LATD = 0b01000000; else if(acq>224 && acq<=256) LATD = 0b10000000;
else LATD = 0b00000000;
}
}
- Scorrimento Analogico LEDs
In questo esercizio, come nel precedente, i registri coinvolti sono, oltre a OSCCON per l’oscillatore di clock, TRISD e LATD per la gestione dei pins collegati ai LEDs, quelli che riguardano l’Acquisizione Analogica, cioè TRISA, ANSEL, ADCON0, ADCON1 e ADCON2
// PIC18F45K20 Configuration Bit Settings // 'C' source line config statements // CONFIG1H #pragma config FOSC = INTIO67 // Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7) #pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled) #pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled) // CONFIG2L #pragma config PWRT = OFF // Power-up Timer Enable bit (PWRT disabled) #pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled)) #pragma config BORV = 18 // Brown Out Reset Voltage bits (VBOR set to 1.8 V nominal) // CONFIG2H #pragma config WDTEN = OFF // Watchdog Timer Enable bit (WDT is controlled by SWDTEN bit of the WDTCON register) #pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768) // CONFIG3H #pragma config CCP2MX = PORTC // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1) #pragma config PBADEN = ON // PORTB A/D Enable bit (PORTB<4:0> pins are configured as analog input channels on Reset) #pragma config LPT1OSC = OFF // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation) #pragma config HFOFST = ON // HFINTOSC Fast Start-up (HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize.) #pragma config MCLRE = ON // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled) // CONFIG4L #pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset) #pragma config LVP = ON // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled) #pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode)) // CONFIG5L #pragma config CP0 = OFF // Code Protection Block 0 (Block 0 (000800-001FFFh) not code-protected) #pragma config CP1 = OFF // Code Protection Block 1 (Block 1 (002000-003FFFh) not code-protected) #pragma config CP2 = OFF // Code Protection Block 2 (Block 2 (004000-005FFFh) not code-protected) #pragma config CP3 = OFF // Code Protection Block 3 (Block 3 (006000-007FFFh) not code-protected) // CONFIG5H #pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected) #pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected) // CONFIG6L #pragma config WRT0 = OFF // Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected) #pragma config WRT1 = OFF // Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected) #pragma config WRT2 = OFF // Write Protection Block 2 (Block 2 (004000-005FFFh) not write-protected) #pragma config WRT3 = OFF // Write Protection Block 3 (Block 3 (006000-007FFFh) not write-protected) // CONFIG6H #pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected) #pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected) #pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected) // CONFIG7L #pragma config EBTR0 = OFF // Table Read Protection Block 0 (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks) #pragma config EBTR1 = OFF // Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks) #pragma config EBTR2 = OFF // Table Read Protection Block 2 (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks) #pragma config EBTR3 = OFF // Table Read Protection Block 3 (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks) // CONFIG7H #pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks) // #pragma config statements should precede project file includes. // Use project enums instead of #define for ON and OFF. #define _XTAL_FREQ 1000000
Il file main.c
/** -------------------- PROGRAMMA Scorrimento Analogico LEDs-------------------- **/
/* Commenti e descrizione al programma */
/** I N C L U D E S **************************************************/
#include <xc.h>
#include "Config.h"
void Setup(void) {
TRISA = 0b00000001; // Set RA0 (aka AN0) come input
TRISD = 0b00000000; // Set RB0-RB8 come Output
OSCCON = 0b00110110; // Internal Osc, 1MHz, F stabile
ANSEL = 0b00000001; // Set AN0 (aka RA0) come analogico
ADCON0 = 0b00000001; // Channel AN0 (xx00 00xx), Enable ADC (xxxx xxx1)
ADCON1 = 0b00000000; // VDD and VSS as voltage reference (xxxx 0000)
ADCON2 = 0b00111000; // Right justify result (1xxx xxx), 2 TAD delay (xx00 1xxx), TAD = 1 us (Fck/16 = 1 Mhz) (xxxx x101)
}
int acq;
void main(void) {
Setup();
while(1){
ADCON0bits.GO = 1; // Start conversion
acq = ADRESH; // Read ADC registers and convert to 0-1023 integer
while(ADCON0bits.GO);
LATD = 0b00000001;
for(int i=1; i<=acq; i++)__delay_ms(2); //_delay_ms() deve avere come parametro una costante, dà errore se gli passiamo direttamente una variabile
LATD = 0b00000010;
for(int i=1; i<=acq; i++)__delay_ms(2);
LATD = 0b00000100;
for(int i=1; i<=acq; i++)__delay_ms(2);
LATD = 0b00001000;
for(int i=1; i<=acq; i++)__delay_ms(2);
LATD = 0b00010000;
for(int i=1; i<=acq; i++)__delay_ms(2);
LATD = 0b00100000;
for(int i=1; i<=acq; i++)__delay_ms(2);
LATD = 0b01000000;
for(int i=1; i<=acq; i++)__delay_ms(2);
LATD = 0b10000000;
for(int i=1; i<=acq; i++)__delay_ms(2);
}
}
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